Measurement-computing CIO-DAS6402/12 Instrukcja Użytkownika Pobierz pdf (Strona 19)

Table 5-2. DAS6402 I/O Map - ENHANCED Mode

(BOLD indicates register definition for DAS6402/16)

8254 Counter Control RegisterNone. No read back on 8254BASE +15

CTR 2 Data - A/D Pacer ClockCTR 2 Data - A/D Pacer ClockBASE +14

CTR 1 Data - A/D Pacer ClockCTR 1 Data - A/D Pacer ClockBASE +13

CTR 0 Data: Preload for residual countCTR 0 Data: (Residual/ End of acq) BASE +12

UB,SEDIFF,MODE,Int source, ADGainUB,SEDIFF,MODE,Int source, ADGainBASE +11

DAC range, Pacer clock controlDAC range, Pacer clock controlBASE +10

Burst Enable, Interrupt, Pacer SourceBurst Enable, Interrupt, Pacer SourceBASE + 9

Extend modes and clear interruptsFIFO, Interrupt Status, Clock rateBASE + 8

D/A 1 Bits 4-11NoneBASE + 7

D/A 1 Bits 0-3NoneBASE + 6

D/A 0 Bits 4-11NoneBASE + 5

D/A 0 Bits 0-3NoneBASE + 4

Digital Output Bits 0-7 Digital Input bits 0-7 / External controlBASE + 3

32/64 Channel Mux (Word) /Reset FIFOPost-Trigger Index CounterBASE + 2

None Do not use, use BASE onlyBASE + 1

Software Start A/D Conversion A/D bits 0(LSB) -15 (MSB) (Word)BASE

Software Start A/D Conversion A/D bits 0(LSB) -11 (MSB) (Word)BASE

WRITE FUNCTIONREAD FUNCTIONADDRESS

5.2 A/D DATA WORD REGISTERS

In Enhanced Mode, two of the data registers are configured for 'Word' reads or writes, as opposed to performing the I/O operation

as separate byte reads or writes. These two registers are the A/D Data Register at the BASE+0, and the Channel Mux Hi/Lo

Register at BASE+2. Any IO accesses (reads or writes) to either of these registers is interpreted by the board as Word IO.

A/D DATA WORD REGISTER - 12 BIT

BASE + 0 Example, 300h, 768 Decimal

READ/WRITE

MA0MA1MA2MA3AD0

LSB

AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11

MSB

COMPATIBLE

0000AD0

LSB

AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11

MSB

ENHANCED

0132456789101112131415Mode

A read/write register. The A/D Data Register is configured as a word because REP INSW can be used to quickly read data from

the board, allowing for higher A/D conversion rates than would be possible if using DMA, which accesses the A/D data as two

bytes.

READ

On read, the 12-bit ADC value is presented in 'left-justified' format, with the most-significant ADC bit occupying the data word

bit position #15; the least-significant ADC bit occupies bit position #4 of the data word.

WRITE

A write to the base address will cause an A/D conversion, (Bits 0&1 of BASE+9 must be 0.)

ENHANCED MODE: The channel tag is not available in enhanced mode, thus the lowest four bits of the data word will be read

back as zero.

COMPATIBLE MODE: The channel tag is available in compatible mode, occupying the lowest four bits of the data word.

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 39 40

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