Measurement-computing CIO-DAS6402/12 Instrukcja Użytkownika Pobierz pdf (Strona 18)

5 REGISTER ARCHITECTURE

5.1 INTRODUCTION

The CIO-DAS6402 is controlled and monitored by reading and writing to 16 I/O addresses. The first address is referred to as the

BASE ADDRESS and is set by a bank of switches on the board. All other addresses are located at the BASE ADDRESS plus a

specified offset.

Registers are easy to read from and write to, though to create a complete data acquisition software program at the register level is a

significant undertaking. Unless there is a specific reason that you need to write your program at the register lever, we recommend

using our Universal Library.

In summary form, the registers and their function are listed on the following table. Within each register are eight bits which may

constitute a byte of data or be eight individual bit set/read functions.

Table 5-1. DAS6402 I/O Map - COMPATIBLE Mode

(BOLD indicates register definition for DAS6402/16)

8254 Counter Control RegisterNone. No read back on 8254BASE +15

CTR 2 Data - A/D Pacer ClockCTR 2 Data - A/D Pacer ClockBASE +14

CTR 1 Data - A/D Pacer ClockCTR 1 Data - A/D Pacer ClockBASE +13

Counter 0 DataCounter 0 DataBASE +12

MODE, A/D Gain ControlDMA, U/B, SEDIFF, MODE, A/D GainBASE +11

DAC range, TRIG0/CTR0DAC range, TRIG0/CTR0BASE +10

DMA Enable, Interrupt, Pacer SourceDMA Enable, Interrupt, Pacer Source BASE + 9

Reset interrupt flip-flopEOC, UNI/BIP, SEDIFF, MuxBASE + 8

D/A 1 Bits 4-11NoneBASE + 7

D/A 1 Bits 0-3NoneBASE + 6

D/A 0 Bits 4-11NoneBASE + 5

D/A 0 Bits 0-3NoneBASE + 4

Digital Output Bits 0-3 Digital Input bits 0-3 / External controlBASE + 3

8/16 Channel Mux / Reset FIFO8/16 Channel Mux BASE + 2

NoneA/D Bits 8 - 15 (MSB)BASE + 1

Software Start A/D ConversionA/D bits 0 (LSB) - 7 BASE

NoneA/D Bits 4 -11 (MSB)BASE + 1

Software Start A/D ConversionA/D bits 0(LSB) - 3 & Channel # BASE

WRITE FUNCTIONREAD FUNCTIONADDRESS

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 39 40

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