Measurement-computing CIO-DAS160x/1x Instrukcja Użytkownika Pobierz pdf (Strona 31)

6.1.10 PACER CLOCK DATA & CONTROL REGISTERS

8254 COUNTER 0 DATA

BASE ADDRESS + Ch

D1D2D3D4D5D6D7D8

01234567

8254 COUNTER 1 DATA

BASE ADDRESS + Dh

D1D2D3D4D5D6D7D8

01234567

8254 COUNTER 2 DATA

BASE ADDRESS + Eh

D1D2D3D4D5D6D7D8

01234567

The three 8254 counter/timer data registers can be written to and read from. Because each counter will

count as high as 64,535, it is clear that loading or reading the counter data must be a multi-step process.

The operation of the 8254 is explained in Intel 8254 data sheet.

8254 COUNTER CONTROL

BASE ADDRESS + Fh

D1D2D3D4D5D6D7D8

01234567

This register controls the operation and loading/reading of the counters. The configuration of the 82C54

codes which control the chip is explained in the Intel 82C54 data sheet.

6.1.11 24-bit DIGITAL I/O REGISTERS (not applicable on -P5 versions)

PORT A DATA

BASE ADDRESS + 400h

D0D1D2D3D4D5D6D7

01234567

PORT B DATA

BASE ADDRESS +401h

B0B1B2B3B4B5B6B7

01234567

Ports A & B can be programmed as input or output. Each is written to and read from in bytes, although

for control and monitoring purposes the individual bits are used.

Bit set/reset and bit read functions require that unwanted bits be masked out of reads and ORed into

writes.

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 43 44

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Measurement-computing CIO-DAS160x/1x Instrukcja Użytkownika Strona 31