Measurement-computing CIO-PDMAxx Instrukcja Użytkownika

CIO-PDMA16&CIO-PDMA32High Speed Digital Input/OutputUser’s ManualRevision 5 September, 2000

4.2 SIGNAL FUNCTIONAL DESCRIPTIONSPositive or negative edge triggered input. Softwareprogrammable.INTERRUPTA low on this signal will hold the gates

When the CIO-PDMA board is used as an output device to send data to another TTLdevice over a standard ribbon cable, it may be necessary to add balanci

5.0 REGISTER MAPS 5.1 CIO-PDMA16 REGISTER MAPThe CIO-PDMA16 and use eight consecutive I/O addresses in the PC's I/O addressspace. The first

Ports A & B are set to input on power-up or hardware reset of the computer. Thedirection of transfer, input/output, is controlled by one bit for e

The DMA control register is cleared on power-up or hardware reset. If you arewriting your own DMA routine, the DMA enable bit should be set before en

5.1.4 8254 COUNTER LOAD & READ REGISTERSCOUNTER 0BASE ADDRESS + 4 304h, 77210D0D1D2D3D4D5D6D701234567COUNTER 1BASE ADDRESS + 5 305h, 77310D0D1D2D

RL1 to RL0 are the read and load control bits:RL1 RL0 OPERATION0 0 Latch counter.0 1 Read/load high byte.1 0 Read/load low byte.1 1 Read/load low then

5.2 CIO-PDMA32 REGISTER MAPThe PDMA-32 boards use 16 consecutive addresses starting at the Base Address inthe computers I/O space, as shown in the fo

Byte-wide DMA or Rep-String operations may be made only through Port A. If bytemode is selected via the DMA Control Register (D2=0), then Port B is av

2. If word mode is selected for regular I/O (D2 = 1), then the B direction bit isignored. Both ports operate as a single 16-bit port with the directi

MEGA-FIFO, the CIO prefix to data acquisition board model numbers, the PCM prefix to dataacquisition board model numbers, PCM-DAS08, PCM-D24C3, PCM-DA

The data in the counter read register, and the action taken on the data in the counterload register, is wholly dependent upon control code written to

5.2.6 DMA Level Select Register The level of DMA request generated by the board is determine via this register. Thisregister is also used to determi

This bit is set when in REP_ENB mode, and the SampleCounter has reached terminal count.REP_DONE0This bit is set when in REP_ENB mode and the FIFO isha

When this bit is set, the OVERRUN and UNDERRUN errorflags are enabled. The error flags should be enabled when aREP transfer size of greater than one F

5.2.11 REP mode ARM register This is a write-only register. In continuous REP mode, a write to this register arms thesample counter. Once armed, the

6.0 SPECIFICATIONS Typical for 25°C unless otherwise specified.Power Consumption+5VDCCIO-PDMA16 850 mA typical, 1.0 A maxCIO-PDMA32 900 mA typica

Data TransferCIO-PDMA16 Interrupt, DMA or software polledCIO-PDMA32 From 512 sample FIFO via REPINSW,interrupt, DMA or software polled DMACIO-PDMA16 C

Counter 2 - CIO-PDMA16 (user counter 3)Source: Counter 0 output.Gate: Pulled high through 10k resistorOutput: Not connectedCounter 2 - CIO-PDMA32 Us

For your notes.24

For your notes.25

216.0 SPECIFICATIONS ...205.2.12 FIFO Register ...205.2.11 REP mode ARM register ...

For your notes.26

EC Declaration of ConformityWe, Measurement Computing Corporation, declare under sole responsibility that theproduct:DescriptionPart NumberHigh speed

Measurement Computing Corporation16 Commerce Boulevard,Middleboro, MA 02346(508) 946-5100Fax: (508) 956-9500E-mail: [email protected].

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1.0 INTRODUCTION The CIO-PDMA16 and CIO-PDMA32 are high speed, 16-bit digital interfaces forISA bus personal computers. The CIO-PDMA16 utilizes 8

2.0 SOFTWARE INSTALLATION Before you open your computer and install the board, install and run InstaCal, theinstallation, calibration and test utilit

Figure 3-1. CIO-PDMA16 Base Address Switches (300h shown) A complete address is constructed by calculating the hexadecimal number whichcorresponds to

3.3 WAIT STATE JUMPERThe CIO-PDMA16 board has a wait state jumper (Figure 3-3) which can enable anon-board wait-state generator. A wait state is an e

4.0 CABLING TO THE CIO-PDMA## 4.1 SIGNAL CONNECTIONSThe CIO-PDMA16 and CIO-PDMA32 connector is a 37-pin D-type connectoraccessible from the rear of t