Measurement-computing CIO-PDMAxx Instrukcja Użytkownika Pobierz pdf (Strona 20)

The data in the counter read register, and the action taken on the data in the counter

load register, is wholly dependent upon control code written to the control register.

The counters are 16 bits, each with an 8-bit window, the read/load register. Data are

shifted into and out of the 16-bit counters through these 8-bit windows according to

the control byte.

5.2.5 Counter Control Register

Base Address + 7

LSBMSB

BCDM0M1M2RL0RL1SC0SC1

01234567

SC1 and SC0 are the counter select bits. The are binary coded between 0 and 2.

SC1 SC2 Counter

0 0 0

0 1 1

1 0 2

RL1 and RL0 are the read and load control bits:

Read/load low then high byte (word transfer).11

Read/load low byte.01

Read/load high byte.10

Latch counter.00

OperationRL0RL1

M2 to M0 are the counter mode control bits:

Counter 0 and Counter 1 are hardware-fixed to operate in Rate Generator mode only.

Rate Generator.010

Operation TypeM0M1M2

Counter 2 can support the following two modes:

Rate Generator.010

Change on terminal count.000

Operation TypeM0M1M2

BCD = 0: The counters are hardware fixed to support 16-bit binary mode only.

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 31 32

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Measurement-computing CIO-PDMAxx Instrukcja Użytkownika Strona 20