Measurement-computing CIO-DAS16 Instrukcja Użytkownika Pobierz pdf (Strona 28)

When TRIG0 = 0, the external trigger at pin 25 has no effect on the GATEs of counter 1 and 2.

See Figure 4-1 for a block diagram of the Pacer Clock logic.

Figure 4-1. Pacer Clock and Control Logic

4.9 BASE + 11 - RESERVED REGISTER

BASE ADDRESS + 11

This address is reserved for use as a programmable gain register in other DAS16 family boards.

4.10 PACER CLOCK DATA & CONTROL REGISTERS

8254 COUNTER 0 DATA

BASE ADDRESS +12

D0D1D2D3D4D5D6D7

01234567

8254 COUNTER 1 DATA

BASE ADDRESS +13

D0D1D2D3D4D5D6D7

01234567

10 MHz

COUNTER 0

COUNTER 2

COUNTER 1

A/D PACER

+5V

10K

+5V

10K

1 /10

CONTROL REGISTER

BASE + 10

CTR0

GATE

OUT

10 MHz

1MHz

+5V

10K

CTR 2 OUT

CTR 0 OUT

TRIGGER

TRIG0

CTR 0 GATE

CTR 0 CLOCK IN

1 2 ... 23 24 25 26 27 28 29 30 31 32 33 34 35 36

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Measurement-computing CIO-DAS16 Instrukcja Użytkownika Strona 28