
Table 4-2. Register Summary
Configure 8255None - No read back on 8255BASE + 19
Port C OutputPort C InputBASE + 18
Port B OutputPort B Input BASE + 17
Port A OutputPort A Input of 8255BASE + 16
Pacer Clock Control (8254)None. No read back on 8254BASE + 15
CTR 2 Data - A/D Pacer CTR 2 Data - A/D Pacer ClockBASE + 14
CTR 1 Data - A/D Pacer CTR 1 Data - A/D Pacer ClockBASE + 13
Counter 0 DataCounter 0 DataBASE + 12
Reserved for future use.BASE + 11
NonePacer clock control register.BASE + 10
Set DMA, INT etcDMA, Interrupt & Trigger ControlBASE + 9
Interrupt ResetStatus EOC, UNI/BIP etc.BASE + 8
D/A 1 Bits 1(MSB) - 8NoneBASE + 7
D/A 1 Bits 9-12 (LSB)NoneBASE + 6
D/A 0 Bits 1(MSB)-8NoneBASE + 5
D/A 0 Bits 9-12 (LSB)NoneBASE + 4
Digital 4 Bit OutputDigital 4 Bit InputBASE + 3
Channel MUX SetChannel MUX ReadBASE + 2
NoneA/D Bits 1 (MSB) - 8BASE + 1
Start A/D FunctionA/D Bits 9 - 12 (LSB) & Channel #BASE
WRITE FUNCTIONREAD FUNCTIONADDRESS
4.2 A/D DATA & CHANNEL REGISTERS
BASE ADDRESS
CH1CH2CH4CH8A/D12
LSB
A/D11A/D10A/D9
01234567
A read/write register.
READ:
On read, it contains two types of data. The least significant four digits of the analog input data and the channel number
which the current data was taken from.
These four bits of analog input data must be combined with the eight bits of analog input data in BASE + 1, forming a
complete 12-bit number. The data is in the format 0 = minus full scale. 4095 = +FS.
The channel number is binary-coded. The weights are shown in Table 4-1. For example, if the current channel were five,
then bits CH4 and CH1 would be high and CH8 and CH2 would be low.
WRITE:
Writing any data to the register causes an immediate A/D conversion.
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