Measurement-computing CIO-PDMAxx Instrukcja Użytkownika Pobierz pdf (Strona 21)

5.2.6 DMA Level Select Register

The level of DMA request generated by the board is determine via this register. This

user programmable.

Base Address + 8

LSBMSB

L0L1L2

xxxxx

01234567

L2, L1, L0 select the DMA level or REP Port size as follows:

000 = Level 0 (byte) 100 = Illegal

001 = Level 1 (byte) 101 = Level 5 (word)

010 = Level 2 (byte) 110 = Level 6 (word)

011 = Level 3 (byte) 111 = Level 7 (word)

x = don’t care

5.2.7 Interrupt Level Register

This is a read/write register used to program the desired interrupt level of the

PDMA-32 board. These bits are cleared after reset. Note that the unused bits D7:D4

are user programmable. Interrupt priorities highest-to-lowest are 9, 10, 11, 12, 14, 15,

3, 4, 5, 6, and 7. There is no interrupt Level 2 on the PC/AT; it is redirected through

Interrupt Level 9.

Base Address + 9

I0I1I2I3

xxxx

01234567

MSB LSB

x = don’t care

5.2.8 Interrupt Status Register

This is a read only register. In DMA mode this register returns a single bit

corresponding to the state of the PDMA-32’s internal interrupt request. In REP mode

this register provides additional flag information regarding the status of the current

REP transfer. Reading the Interrupt Status Register will clear the pending interrupt

request and re-enable interrupts.

Base Address + Ah

REP_DONEREP_FLGOVERRUNUNDER

RUN

000

IRQ

01234567

MSB LSB

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 31 32

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Measurement-computing CIO-PDMAxx Instrukcja Użytkownika Strona 21