Measurement-computing PC104-DAS16JR/12 Instrukcja Użytkownika Pobierz pdf (Strona 20)

3.6 DMA, INTERRUPT & TRIGGER CONTROL

BASE ADDRESS + 9

TS0TS1DMADon’t

Care

IR1IR2IR4INTE

01234567

A read and write register.

READ

INTE = 1, Interrupts are enabled. An interrupt generated will be placed on the

PC bus interrupt level selected by IR4, IR2 & IR1. INTE = 0, interrupts are

disabled.

IR4, IR2, IR1 are bits in a binary number between 0 and 7 which map interrupts

onto the PC bus interrupt levels 2 - 7. Interrupts 0 & 1 may not be asserted by the

PC104-DAS16Jr/xx.

DMA = 1, DMA transfers are enabled. DMA = 0, DMA transfers are disabled.

It is worth noting that this bit only allows the PC104-DAS16Jr/xx to assert a

DMA request to the PC on the DMA request level selected by the DMA switch

on the PC104-DAS16Jr/xx. Before this bit is set to 1, the PC's 8237 (or

appropriate) DMA controller chip must be set up.

TS1 & TS0 control the source of the A/D start conversion trigger according to

Table 4-4 below.

Table 3-3. A/D Start Conversion Source Coding

Start on Pacer Clock Pulse (CTR 2 OUT, no external

access)

Start on rising TRIGGER (Digital input 0, Pin 25)01

Software triggered A/D only.X0

TS0TS1

1 2 ... 15 16 17 18 19 20 21 22 23 24 25 ... 31 32

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Measurement-computing PC104-DAS16JR/12 Instrukcja Użytkownika Strona 20