Measurement-computing PC104-DAS16JR/12 Instrukcja Użytkownika Strona 1

PC104-DAS16Jr/12& PC104-DAS16Jr/16User’s ManualRevision 4August, 2001

If compatibility with the CIO-DAS16 series connector is desired, you can convert to acompatible 37D connector using the C40-37F-# or C40-37M-# cables.

The BP40-37 Adapter connector accepts female 37-pin, D-type connectors, such asthose on the C37FF-2, 2 foot cable with connectors (Figure 2-3). If fr

2.3 SINGLE-ENDEDA single-ended input is two wires connected to the board, a channel high (CH# HIGH)and a Low Level Ground (LLGND). The LLGND signal m

A floating differential hookup is handy when the signal source is floating with respectto ground, such as a battery, 4-20 mA transmitter or and the le

2.5 DIFFERENTIAL INPUTA differential signal has three wires from the signal source. The signals are Signal Figure 2-6. Differential ConnectionsHigh (

3 REGISTER ARCHITECTURE3.1 CONTROL & DATA REGISTERSThe PC104-DAS16Jr/xx is controlled and monitored by writing to and reading from16 consecutive 8

Table 3-2. Register SummaryPacer Clock Control (8254)None. No read back on 8254.BASE + 15CTR 2 Data - A/D PacerCTR 2 Data- A/D Pacer ClockBASE + 14CTR

WRITEWriting any data to the register causes an immediate A/D conversion.3.2.2 16-BIT BOARDSA/D15LSBA/D14A/D13A/D12A/D11A/D10A/D9A/D801234567A read/wr

WRITEThe channel scan limits desired are written as one byte. The high channel numberscan limit is in the most significant 4 bits. The low channel s

3.5 STATUS REGISTERBASE ADDRESS + 8CH1CH2CH4CH8INTMUXU/BEOC01234567A read mostly, one-function-write register.READEOC = 1, the A/D converter is busy.

MEGA-FIFO, the CIO prefix to data acquisition board model numbers, the PCM prefix to dataacquisition board model numbers, PCM-DAS08, PCM-D24C3, PCM-DA

3.6 DMA, INTERRUPT & TRIGGER CONTROLBASE ADDRESS + 9TS0TS1DMADon’tCareIR1IR2IR4INTE01234567A read and write register.READINTE = 1, Interrupts are

3.7 PACER CLOCK CONTROL REGISTERBASE ADDRESS + 10TRIG0CTR0XXXXXX01234567WRITE onlyCTR0 = 1. When CTR0 = 1, an on-board 100 kHz clock signal is ANDed

3.8 ANALOG INPUT RANGE REGISTERBASE ADDRESS + 11G0G1Uni/BipRangeXXXX01234567Table 3-4. Input Range Codes PC104-DAS16Jr/1270 to 1.25V111060 to 2.5V0110

8254 COUNTER 1 DATABASE ADDRESS + 13 30Dh, 781 decimalD1D2D3D4D5D6D7D8012345678254 COUNTER 2 DATABASE ADDRESS + 14 30Eh, 782 decimalD1D2D3D4D5D6D7D8

Therefore the maximum sampling rate of the PC104-DAS16Jr/xx is dependent on thecomputer.3.11 DIGITAL INPUT & OUTPUTThere are four bits of output o

4 SPECIFICATIONS Power consumption+5VDC quiescentPC104-DAS16Jr/12 140 mA typical, 230 mA maxPC104-DAS16Jr/16 145 mA typical, 205 mA max+ 5VDC Ope

A/D conversion timePC104-DAS16Jr/12 3.3 µsPC104-DAS16Jr/16 10 µsThroughputPC104-DAS16Jr/12 150 kHzPC104-DAS16Jr/16 100 kHzAccuracyPC104-DAS16Jr/12 0.0

Counter sectionCounter type 82C54Configuration 3 down-counters, 16 bits eachCounter 0 - Independent user counterSource: Programmable (external or 100

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Table of Contents214 SPECIFICATIONS ...203.11 DIGITAL INPUT & OUTPUT ...

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EC Declaration of ConformityWe, Measurement Computing Corporation., declare under sole responsibility that theproduct:DescriptionPart NumberAnalog inp

Measurement Computing Corporation16 Commerce Boulevard,Middleboro, Massachusetts 02346(508) 946-5100Fax: (508) 946-9500E-mail: info@measurementcomputi

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1 INSTALLATION1.1 SOFTWAREBefore you open your computer and install the board, install and run InstaCal™, theinstallation, calibration and test utilit

Figure 1-2. PC104-DAS16Jr/16 Switch and Jumper Locations1.3 BASE ADDRESSThe base address switches are set at the factoryto address 300h (768 decimal)

1.4 DMA LEVEL SELECTIf using an XT PC there are only two DMA levels available and level 3 is probablyused by the hard disk controller. Set the DMA le

Older software may require the 1 MHz setting for this jumper. Use the 10MHz settingfor any new software development to get better resolution setting

2 SIGNAL CONNECTIONS2.1 CONNECTOR DIAGRAMThe PC104-DAS16Jr/xx analog connector is a 40-pin in-line header connector (Figure2-1). This connector accep