Measurement-computing CIO-CTRxxHD Instrukcja Użytkownika Pobierz pdf (Strona 11)

5.2 BASE +400 hex & BASE +401 hex

BASE + 400 controls the wait state for the board and the clock source and interrupt

level for 9513 #1 and 9513 #2

L0L1L2CLK00CLK01CLK10CLK11WSEN

D0D1D2D3D4D5D6D7

BASE +401 controls the clock source and interrupt level for 9513 #3 and 9513 #4

L0L1L2CLK00CLK01CLK10CLK11X

D0D1D2D3D4D5D6D7

Read

- No read function for these registers.

Write

- L0, L1, and L2 select IRQ as follows:

Table 5-2. IRQ Select Codes

7111

6011

5101

4001

3110

2010

N/A100

N/A000

IRQL0L1L2

For BASE +400, CLK0# selects the clock cource for 9513 #1 (the chip designated

“U1”), CLK1# selects the clock source for 9513 #2 (the chip designated “U2”)

For BASE +401, CLK0# selects the clock cource for 9513 #3 (the chip designated

“U3” for the CIO-CTR20HD”), CLK1# selects the clock source for 9513 #4 (the chip

designated “U4” for the CIO-CTR20HD).

Table 5-3. Clock-Select Codes

N/A11

External01

5 MHz10

1 MHz00

CLOCK SOURCECLK#0CLK#1

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 19 20

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